The present invention generally relates to a system for removing material from a wafer and, in particular, relates to one such system including means for removing material from a wafer in accordance with a predetermined profile.
There are many instances, particularly in the semiconductor arts, where it is desirable to remove material in a controlled manner. Hence, although the following discussion relates to one type of semiconductor structure to which this system is particularly applicable it will be understood that this semiconductor application is not considered as being limiting.
Conventional semiconductor devices are most frequently fabricated in a layer of high resistivity semiconductor material, usually silicon, by such methods as diffusion, epitaxial layer growth, ion implantation or perhaps a combination of these techniques.
While this generalized configuration has served the semiconductor industry quite well for numerous years, it nonetheless has several drawbacks. For example, the small, but finite, conductivity of the high resistivity silicon creates charge leakage paths that limit the circuits that can be achieved. That is, devices operating under applied potentials of several hundred volts cannot be fabricated on the same device chip with devices operating at only a few volts.
In addition, the charge leakage paths also limit the circuits that can be achieved in both device density and bit storage lifetimes.
The proximity of the bulk silicon wafer to the active device layer results in a reduced radiation hardness. That is, for a memory device, exposure to high radiation can result in "bit errors". Whereas the thin active device layer is substantially transparent to incident radiation the much thicker underlying wafer absorbs a substantial amount of such radiation. This high absorption results in free electrical carriers that migrate to the active device layer and create logic and/or memory errors.
It has been long recognized by the industry that many of these problems could be completely eliminated or, at least, substantially reduced by forming the active device layer in a very thin layer of semiconductor that is supported by an insulator rather than the bulk silicon. Such a configuration is generally referred to as silicon-on-insulator (SOI).
Historically, SOI efforts have been directed to producing circuits in silicon-on-sapphire substrates. In general, the process would start with a single crystal sapphire wafer oriented such that the crystalline direction corresponding to the wafer surface represented the best possible lattice match to silicon. Then, a single crystal silicon film would be epitaxially grown on that surface. Nonetheless, in such a process there remains a substantial lattice mismatch between the sapphire and the silicon. Consequently, such devices generally exhibit relatively high defect densities. Further, silicon-on-sapphire wafers are brittle and comparatively quite expensive compared to the standard silicon wafers.
As a result, attempts have been made to produce silicon films on a silicon wafer, but with a layer of insulating material, i.e. , silicon dioxide or silicon nitride, or the like, therebetween.
One of the earlier methods attempted is commonly referred to as zone-melt recrystallization (ZMR). In this technique a polycrystalline silicon film is deposited on a thermally oxidized silicon wafer surface, the film and wafer are then locally heated to reduce recrystallization of the silicon film. The resulting film is not a single crystal but, rather, consists of a large number of grains. Due to the large lattice mismatch between the silicon and the insulator the resulting film have substantially higher defect densities and rougher surfaces than typical high quality bulk silicon and thus exhibit poorer electrical properties.
A more recent development in the silicon-on-insulator field is referred to as the separation by implanted oxygen (SIMOX) . In this technique a buried oxide layer is formed in a bulk silicon wafer by implanting oxygen ions to a depth of between 3000 .ANG. to 4000 .ANG. beneath the wafer surface. This results in a thin silicon layer above the oxide. The thin silicon layer is thus physically and electrically isolated from the bulk wafer. However, such wafers exhibit substantially higher impurity levels than bulk silicon which high impurity levels are quite disastrous for device performance. Further, the buried oxide layer typically contains numerous precipitates, resulting in lower breakdown voltage levels than for high quality thermal silicon dioxide layers. Still further, the cost of a finished SIMOX wafer is about 100 times more expensive than a conventional bulk wafer and about 10 times greater than a bonded silicon on insulator wafer.
Most recently SOI wafers have been formed by using two standard silicon wafers. One standard wafer is, typically, thermally oxidized to provide a silicon dioxide layer of about one micrometer on both surfaces thereof. The oxidized wafer is then bonded to a polished surface of the other standard silicon wafer. The bonded assembly is thereafter thinned by a series of mechanical grinding and chemo-mechanical polishing steps applied to its unbonded surface. The thinning process currently involves, in essence, standard mechanical grinding and polishing steps wherein material is removed from the wafer simultaneously for all surface points, i.e., full wafer abrasive removal with a polishing tool at least as large as the wafer itself. The process utilizes the interface between the back surface of the base wafer and the grinding/polishing lap as a reference for achieving a flat upper surface of the wafer into which devices will be formed. This process, thus, assumes that both the base wafer back surface and the lap are initially very flat and that there is not particulate contamination therebetween.
As it happens, such wafers exhibit several micrometer of peak-to-valley non-flatness across the surfaces. Further, it is extremely difficult to eliminate particulate contamination during thinning. Still further, whole wafer grinding and polishing processes are prone to an edge-roll off effect created by the deformation of the mechanical polishing tool under pressure as it traverses beyond the edge of the wafer being polished. In addition, the creation of an absolutely flat upper surface on the bonded wafer does not ensure a uniform thickness of the silicon film if there are any thickness variations in the underlying oxide or wafer bond. Finally, the use of full surface grinding and polishing techniques does not permit any useful control over the final thickness profile of the resultant thinned wafer.
Consequently, there is a substantial need for a system for removing material from wafers that overcomes the above-recited drawbacks of the current technology.